МОДЕЛЮВАННЯ РОБОТИ ПОМНОЖУВАЧA В КРИТИЧНИХ ЗАСТОСУВАННЯХ
Анотація
Досліджено критичні застосування помножувача мантис, що виконує ключову операцію в обробці наближених даних. Розроблено програмні мо-делі та виконано моделювання помножувача мантис і його систем контро-лю у випадках кратних несправностей, які можуть виникати в аварійному режимі в умовах накопичення несправностей у нормальному режимі сис- тем критичного застосування. Одержано результати моделювання для мажоритарної структури та її окремих каналів множення, а також мат-ричного помножувача мантис із повним та скороченим виконанням опе-рацій і системами контролю за модулем, нерівностями та власними забо-роненими значеннями добутку. Оцінено достовірність результатів мажо-ритарної системи й достовірність задіяних методів контролю.
Посилання
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26. Delphi 10 Seattle: Embarcadero (2015), available at: https://www.embarcadero.com/ru/products/delphi
2. IEC 61508-1:2010 (2010), Functional safety of electrical / electronic / programmable electronic safety related systems. Part 1: General requirements. International Electrotechnical Commission, Geneva [Switzerland].
3. ANSI/IEEE Std 754-1985 (1985), IEEE Standard for Binary Floating-Point Arithmetic.
4. IEEE Std 754™-2008 (2008), (Revision of IEEE Std 754-1985) IEEE Standard for Floating-Point Arithmetic. IEEE 3 Park Avenue New York, NY 10016-5997 [USA].
5. Kharchenko V. S. and other, Sklyar V. V. (edits) (2008), FPGA-based NPP I&C Systems: Development and Safety Assessment, RPC Radiy, Press National Aerospace University “KhAI”, SSTC on Nuclear and Radiation Safety, 188 p. [Ukraine].
6. Drozd M. and Drozd A. (2014), “Safety-Related Instrumentation and Control Systems and a Problem of the Hidden Faults”, The 10th International Conference on Digital Technologies, Zhilina, pp. 137–140 [Slovak Republic].
7. Drozd J., Drozd A. and Antoshchuk S. (2017), “Green IT engineering in the view of resource-based approach”, In: Kharchenko, V., Kondratenko, Y., Kacprzyk, J. (eds.) Green IT Engineering: Concepts, Models, Complex Systems Architectures, Studies in Systems, Decision and Control, vol. 74, pp. 43–65. Springer International Publishing, Heidelberg [Germany].
8. Hiromoto R. (2016), “Parallelism and complexity of a small-world network model”, International Journal of Computing, vol. 15, issue 2, pp. 72–83.
9. NVIDIA Corporation (2007), NVIDIA CUDA Compute Unified Device Architecture, Programming Guide, Version 1.0.
10. Andrecut M. (2009), “Parallel GPU implementation of iterative PCA algorithms”, Journal of Computational Biology, vol. 16, no. 11, pp. 1593–1599, available at: http://dx.doi.org/10.1089/cmb.2008.0221
11. Kharchenko V. S., Siora A. A. and Bakhmach E. S. (2009), “Diversity-Scalable Decisions for FPGA-based Safety-Critical I&Cs: from Theory to Implementation”, Sixth ANS International Topical Meeting on Nuclear Plant Instrumentation, Control, and Human-Machine Interface Technologies (NPI–HMIT 2009) April 5–9, Knoxville, Tennessee [USA].
12. Asad H. and Gashi I. (2014), Diversity in Open Source Intrusion Detection Systems. Computer Safety, Reliability, and Security, Lecture Notes in Computer Science, 8666, Springer, pp. 267–281.
13. Nicolaidis M. and Zorian Y. (1998), “On-Line Testing for VLSI”, a Compendium of Approaches. Electronic Testing: Theory and Application. JETTA, vol. 12, pp. 7–20.
14. Metra C., Schiano L., Favalli M. and Ricco B. (2002), “SelfChecking scheme for the on-line testing of power supply noise”, Proc. of Design, Automation and Test in Europe Conference, pp. 832–836, Paris [France].
15. Omondi A. and Premkumar B. (2007), Residue Number Systems: Theory and Implementation. Imperial College Press, London, 296 p. [UK].
16. Drozd O., Al-dhabi M., Antoshchuk S., Martinyuk O. and Drozd M. (2017), “Models and Methods Checking Mantissas by Inequalities for On-Line Testing of Digital Circuits in Critical Applications”, Proc. IEEE East-West Design & Test Symposium, Novi Sad, pp. 440–444 [Serbia].
17. Saposhnikov V., Dmitriev M. and Goessel M. (1996), “Self-dual parity checking – a new method for on-line testing”, Proc. IEEE VLSI Test Symposium, pp. 162–168.
18. Drozd A. V. (2000), “Efficient Method of Failure Detection in Iterative Array Multiplier”, Design, Automation and Test in Europe. Conference and Exhibition 2000, Paris, p. 764 [France],
19. Intel Quartus Prime Standard Edition User Guide: Getting Started, available at: https://www.intel.com/content/www/us/en/programmable/ documentation/ yoq1529444104707.html
20. MAX 10 FPGA Device Architecture, available at: https://www.intel. com/content/www/us/en/programmable/documentation/sss1397439908414.html
21. Park H. (2007), Truncated Multiplications and Divisions for the Negative Two's Complement Number System, Ph.D. Dissertation. The University of Texas at Austin, Austin [USA].
22. Garofalo V. (2008), Truncated Binary Multipliers with Minimum Mean Square Error: Analytical Characterization, Circuit Implementation and Applications, Ph.D. Dissertation, University of Studies of Naples “Federico II”, Naples [Italy].
23. Nicolaidis M., Manich S. and Figueras J. (1996), “Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations”, Proc. European Design and Test Conference, pp. 186–193, Paris [France].
24. Pleskacz W., Jenihhin M., Raik J., Rakowski M., Ubar R. and Kuzmicz W. (2008), “Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC”, 11th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp. 729–734, Parma [Italy].
25. Drozd A. V., Lobachev M. V. and Hassonah W. (1996), “Hardware check of Arithmetic Devices with Abridged Execution of Operations”, the European Design & Test Conference (ED & TC 96), p. 611, Paris [France].
26. Delphi 10 Seattle: Embarcadero (2015), available at: https://www.embarcadero.com/ru/products/delphi
Опубліковано
2019-12-13
Як цитувати
Drozd, O. V., Vysochyna, P. V., Dombrovskyi, V. Y., Smishchuk, K. V., & Shalak, O. O. (2019). МОДЕЛЮВАННЯ РОБОТИ ПОМНОЖУВАЧA В КРИТИЧНИХ ЗАСТОСУВАННЯХ. Системи та технології, 2(58), 115-125. https://doi.org/10.32836/2521-6643-2019-2-58-7
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