The method for stego-path formation in solving the problem of monitoring the integrity of the program code of FPGA-based devices

K. V. Zashcholkin; O.V. Drozd; J. Y. Sulima; O. M. Ivanova

doi:10.32836/2521-6643-2018-1-56-1

K. V. Zashcholkin Associate Professor of the Department of Computer Intellectual Systems and Networks, Odessa National Polytechnic University, Ukraine, Odessa/
O.V. Drozd Professor of the Department of Computer Intellectual Systems and Networks, Odessa National Polytechnic University, Ukraine, Odessa/
J. Y. Sulima Head of the Electronic and Refrigeration Department, Odessa Technical College of the Odessa National Academy of Food Technologies, Ukraine
O. M. Ivanova Senior lecturer of the Department of Computer Systems, Odessa National Polytechnic University, Ukraine, Odessa,

DOI: https://doi.org/10.32836/2521-6643-2018-1-56-1

Keywords: integrity monitoring; FPGA; LUT; digital watermark; ste-ganographic path; programmable computing units.

Abstract

Issues of program code integrity monitoring of the FPGA-based components of computer systems is considered. As the most effective, the approach is chosen in which the control hash sum is embedded in the monitored information object as a digital watermark. This makes it possible to hide the fact that integrity monitoring is performed, as well as to hide the hash sum by which integrity is monitored. The dis-advantage of the existing methods is that they do not specify the way of forming in the informational object a sequence of elementary units into which the digits of the digi-tal watermark are embedded.
A method for forming in the space of a LUT-container (LUT – Look Up Table) the FPGA chip of a steganographic path (stego-path) of embedding the digital water-mark is proposed. Stego-path is an ordered set of elementary computational LUT units, into the program codes of which the direct embedding of the digits of the digital wa-termark is performed. The paper substantiates the basic theoretical propositions of the proposed method, and formulates a sequence of stages for its implementation. The method determines the way and source of the ordering of the set of LUT units. The method also formalizes the natural constraints on the choice of LUT units for the stego-path. These natural constraints are due to the structure of the LUT-container. The method also defines artificial constraints on the choice of LUT units, which are caused by the bounding components of the stego-key. A rule is established that makes it possible to decide on the inclusion of a LUT unit in the stego path, depending on the connections with the blocks already included in the stego path. The theoretical posi-tions of the method form a cyclic sequence of actions for choosing LUT units from the available set of LUT-container units.
A software implementation of the method is proposed, based on the analysis of the information model of the LUT-container obtained using the CAD system Intel Quartus Prime. The implementation of the proposed method can be used as part of software systems that perform automated monitoring of the integrity of the program code of FPGA-based components.